-- Logic Unit
-- AND	00
-- OR		01
-- XOR	10
-- NOR	11
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------

entity LOGIC_Unit is
	port(
		OP :  in 	std_logic_vector(1 downto 0);
		A 	: 	in 	std_logic_vector(31 downto 0);
		B 	: 	in 	std_logic_vector(31 downto 0);
		S 	: 	out 	std_logic_vector(31 downto 0)
	);
end LOGIC_Unit;

architecture Structural of LOGIC_Unit is

	component XOR_Gate_32Bits is
		port(
			A 	: 	in 	std_logic_vector(31 downto 0);
			B 	: 	in 	std_logic_vector(31 downto 0);
			S 	: 	out 	std_logic_vector(31 downto 0)
		);
	end component;
	
	----------------------------------------------------------------------------------
	
	component AND_Gate_32Bits is
		port(
			A 	: 	in 	std_logic_vector(31 downto 0);
			B 	: 	in 	std_logic_vector(31 downto 0);
			S 	: 	out 	std_logic_vector(31 downto 0)
		);
	end component;
	
	----------------------------------------------------------------------------------
	
	component OR_Gate_32Bits is
		port(
			A 	: 	in 	std_logic_vector(31 downto 0);
			B 	: 	in 	std_logic_vector(31 downto 0);
			S 	: 	out 	std_logic_vector(31 downto 0)
		);
	end component;
	
	----------------------------------------------------------------------------------
	
	component MUX_1_OF_4 is
		port(
			A 		:	in 	std_logic_vector(31 downto 0);
			B 		:	in 	std_logic_vector(31 downto 0);
			C 		: 	in 	std_logic_vector(31 downto 0);
			D 		:	in 	std_logic_vector(31 downto 0);
			SEL 	:	in 	std_logic_vector(1 downto 0);
			Y		:	out 	std_logic_vector(31 downto 0)
		);
	end component;
	
	----------------------------------------------------------------------------------

	signal AND_OUT : std_logic_vector(31 downto 0);
	signal OR_OUT  : std_logic_vector(31 downto 0);
	signal XOR_OUT : std_logic_vector(31 downto 0);
	signal NOR_OUT : std_logic_vector(31 downto 0);
	
	----------------------------------------------------------------------------------
	
begin

	and_inst : AND_Gate_32Bits
		port map(
			A => A,
			B => B,
			S => AND_OUT
		);
		
	or_inst : OR_Gate_32Bits
		port map(
			A => A,
			B => B,
			S => OR_OUT
		);
		
	xor_inst : XOR_Gate_32Bits
		port map(
			A => A,
			B => B,
			S => XOR_OUT
		);
		
	mux_inst : MUX_1_OF_4
		port map(
			A 		=>		AND_OUT,
			B 		=>		OR_OUT,
			C 		=>		XOR_OUT,
			D 		=>		NOR_OUT,
			SEL 	=>		OP,
			Y 		=>		S
		);
		
		NOR_OUT <= not OR_OUT;
		
end Structural;

